Semiconductor device including thin film transistor

ABSTRACT

A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first insulation film formed on the semiconductor substrate, a gate electrode and a second insulation film formed in sequence on the first insulation film, a trench being formed to extend through the second insulation film, the gate electrode and the first insulation film to an interior of the semiconductor substrate. A cylindrical gate insulation film is formed on a surface of the gate electrode which is exposed in the trench. A capacitor insulation film is formed on a surface of the semiconductor substrate exposed in the trench. A cylindrical conductive film is formed inside these insulation films. The cylindrical conductive film includes a region doped with an impurity of the first conductivity type and formed on a surface of the gate insulation film, a region doped with an impurity of a second conductivity type and formed on a surface of the second insulation film and a region doped with an impurity of the second conductivity type and formed on a surface of the capacitor insulation film. A conductive column is formed in a region surrounded by the cylindrical conductive film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor device, andmore particularly to a cell structure of a DRAM (Dynamic Random Accessread and write Memory) using a thin film transistor.

2. Description of the Related Art

In recent years, the demand for greater integration of semiconductordevices has been increasing, as the devices become more and more refinedin size and detail.

To meet the demand, a so-called ring channel TFT (Thin Film Transistor)having a cylindrical channel region has been proposed. FIG. 1A shows alongitudinal cross-sectional view of a conventional ring channel TFT. Acylindrical conductive layer 1 is formed of doped Si. The interior ofthe cylindrical conductive film is hollow. It is possible for theinterior to be filled with a silicon oxide film (not shown). In theconductive film 1, a channel region 1b doped with a P-type impurity isformed between an N-type drain region 1a and an N-type source region 1c.

FIG. 1B is a cross sectional view of the cylindrical channel regiontaken along the line 1B--1B of FIG. 1A. As shown in FIG. 1B, a gateinsulation film 2 and a ring-shaped gate electrode 3 made of conductivepolycrystalline silicon are formed in this order on the outer surface ofthe cylindrical channel region lb.

FIGS. 2A to 2C show the cell structure of a DRAM containing theconventional ring channel TFT shown in FIGS. 1A and 1B.

As shown in FIG. 2A, a first insulation film 6 is formed on a surface ofa P-type silicon substrate 5. A gate electrode 3, having a predeterminedpattern, is formed on the first insulation film 6 and serves as a wordline. A second insulation film 7 is formed on the gate electrode 3 andthe first insulation film 6. A gate insulation film 2 is formed insidethe trench 8 formed to a predetermined depth in the substrate 5 so as tocover the gate electrode 3. A capacitor insulation film 9 is formed on aside wall of the trench 8 in the substrate.

A doped Si film 1 is continuously formed on an upper surface of thesecond insulation film 7 and an inner surface of the trench 8. A hollowportion remains in the trench 8, but can be filed with a silicon oxidefilm (not shown), if necessary.

A region 1b of the doped Si film 1, which is formed on the gateinsulation film 2, is doped with a P-type impurity and serves as achannel. The other portion of the doped Si film 1 is doped with anN-type impurity. An upper portion of the doped Si film above the channelregion 1b is a drain region la and a lower portion of the doped Si filmunder the channel region 1b is a source region 1c.

A region 1e of the doped Si film 1, which is formed on the secondinsulation film 7, serves as a bit line. The portion of the sourceregion 1c, which is in contact with the capacitor insulation film 9,serves as a charge storage layer. An N⁺ region 10 is formed under thetrench 8 in the substrate.

FIGS. 2B and 2C are cross-sectional views of the DRAM shown in FIG. 2A,taken along the lines 2B--2B and 2C--2C, respectively. As shown in FIG.2B, the gate insulation film 2 and the gate electrode 3 are formed onthe outer surface of the cylindrical channel region in this order in across section including the channel region 1b. As shown in FIG. 2C, thecapacitor insulation film 9 covers an outer surface of a charge storagelayer 1d.

The gate electrode 3, the gate insulation film 2, the channel region 1b,the drain region la and the source region 1c constitute a ring channelTFT 11. The silicon substrate 5, the capacitor insulation film 9 and thecharge storage layer 1d constitute a cell capacitor 12.

FIG. 3 shows an equivalent circuit of the DRAM shown in FIG. 2. The wordline 3 is electrically connected to a gate electrode of the ring channelTFT 11. Drain and source regions of the ring channel TFT 11 areelectrically connected to the bit line 1e and the charge storage layer1d of the cell capacitor 12, respectively.

As described above, in the conventional ring channel TFT, the channelregion is in contact with only the gate insulation film on the outerperiphery thereof and the drain and the source regions formed in anupper level and in a lower level of the channel region. For this reason,it is difficult to apply a back gate bias to the channel region and asufficient cut-off characteristic cannot be obtained.

Further, in the DRAM having the conventional ring channel TFT, it isdifficult to obtain a sufficient capacitance by means of the capacitor12 comprised of the silicon substrate 5, the capacitor insulation film 9and the charge storage layer 1d.

SUMMARY OF THE INVENTION

It is accordingly an object of the present invention to provide asemiconductor device in which the integration density of DRAMs can beincreased, the cut-off characteristic of a transistor can be improvedand a sufficient capacitance of the capacitor can be maintained.

According to an aspect of the present invention, there is provided asemiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a first insulation film formed on a surface of the semiconductorsubstrate;

a gate electrode formed on the first insulation film;

a second insulation film formed on the first insulation film and thegate electrode;

a cylindrical gate insulation film formed on a surface of the gateelectrode which is exposed in a trench formed to extend through thesecond insulation film, the gate electrode and the first insulation filmto an interior of the semiconductor substrate;

a capacitor insulation film formed on a surface of the semiconductorsubstrate which is exposed in the trench;

a cylindrical conductive film including a region doped with an impurityof the first conductivity type and formed on the gate insulation film, aregion doped with an impurity of a second conductivity type and formedon a surface of the second insulation film which is exposed in thetrench and a region doped with an impurity of the second conductivitytype and formed on the capacitor insulation film; and

a conductive column formed in a region surrounded by the cylindricalconductive film.

According to another aspect of the present invention, there is provideda semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a first insulation film formed on a surface of the semiconductorsubstrate;

a gate electrode formed on the first insulation film;

a second insulation film formed on the first insulation film and thegate electrode;

a cylindrical gate insulation film formed on a surface of the gateelectrode which is exposed in a trench formed to extend through thesecond insulation film, the gate electrode and the first insulation filmto an interior of the semiconductor substrate;

a capacitor insulation film formed on a surface of the semiconductorsubstrate which is exposed in the trench;

a cylindrical conductive film including a region doped with an impurityof the first conductivity type and formed on the gate insulation film, aregion doped with an impurity of a second conductivity type and formedon a surface of the second insulation film which is exposed in thetrench and a region doped with an impurity of the second conductivitytype and formed on the capacitor insulation film;

a cylindrical third insulation film formed on an inner surface of thecylindrical conductive film; and

a conductive column formed in a region surrounded by the cylindricalthird insulation film.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed out in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIGS. 1A and 1B are cross-sectional views of a conventional ring channelTFT;

FIGS. 2A to 2C are cross sectional views of a DRAM including theconventional ring channel TFT;

FIG. 3 is a diagram showing an equivalent circuit of the DRAM includingthe conventional ring channel TFT;

FIGS. 4A to 7C are cross-sectional views showing

FIGS. 8A to 8E are cross-sectional views showing steps of fabricating asemiconductor device according to a second embodiment of the presentinvention; and

FIGS. 9A to 9C are cross-sectional views showing steps of fabricating asemiconductor device according to a third embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In a semiconductor device of the present invention, a channel region isformed in a cylindrical conductive film and a conductive column made of,for example, monocrystalline silicon doped with an impurity, is formedin the center bore of the cylindrical film. When a bias is applied tothe conductive column, a back gate bias can easily be applied to thechannel region, which was difficult in the conventional semiconductordevice. Accordingly, the present invention allows improvement of thecut-off characteristic of a transistor.

In particular, if the conductive column is electrically connected to asemiconductor substrate, the back gate bias can be applied from thesubstrate to the channel region.

Further, since a PN junction is formed between the conductive column anda cylindrical conductive film situated in the outer periphery of thecolumn, it is possible to obtain a PN junction capacitance. Moreover, ifan insulation film is formed between the cylindrical conductive film andthe conductive column, the area of a capacitor can be increased. In anycase, the capacitance of the capacitor can be increased by virtue of theconductive column formed in the center bore of the cylindricalconductive film.

Embodiments of the present invention will now be described in detailwith reference to the accompanying drawings.

EXAMPLE 1

FIGS. 4A to 7H show steps of fabricating a semiconductor deviceaccording to a first embodiment of the present invention. First, asshown in FIG. 4A, a first insulation film 22 made of SiO₂ or the like isformed on a surface of a P-type Si substrate 21 by, for example, a CVDmethod. Subsequently, a film of a conductive material (e.g.,polycrystalline silicon) is deposited on the first insulation film 22by, for example, an LPCVD method and then patterned, thereby forming agate electrode 23 serving as a word line. Further, a second insulationfilm 24 made of SiO₂ or the like is formed on the gate electrode 23 andthe first insulation film 22 by, for example, the CVD method.

The cross section of the structure of FIG. 4A taken along the line4B--4B is shown in FIG. 4B. In other words, the longitudinal crosssection as shown in FIG. 4A corresponds to the cross section of thestructure of FIG. 4B taken along the line 4A--4A.

In a subsequent step, as shown in FIG. 5A, a trench 25 is formed throughthe second insulation film 24, the gate electrode 23 and the firstinsulation film 22, so as to extend to a predetermined depth in thesubstrate 21, by an RIE (Reactive Ion Etching) method or the like.

The cross section of the structure of FIG. 5A taken along the line5B--5B is shown in FIG. 5B. In other words, the longitudinal crosssection as shown in FIG. 5A corresponds to the cross section of thestructure of FIG. 5B taken along the line 5A--5A.

In a subsequent step, about 10 nm insulation film made of SiO₂ areformed on the interior surface of the trench 25 by, for example, thermaloxidation. That is, as shown in FIG. 6A, a gate insulation film 26 isformed 10 on the surface of the gate electrode 23 which is exposed inthe trench 25 and a capacitor insulation film 27 is formed on thesurface of the substrate 21 which is exposed in the trench 25.

In a subsequent step, an undoped Si film 28 is formed on the interiorsurface of the trench 25 and the upper surface of the second insulationfilm 24 by the CVD method or the like such that a space remains in thetrench 25. Further, an etching-resistive mask 29, made of, for example,SiO₂, is formed on an upper surface of the undoped Si film 28 above thesecond insulation film 24 by, for example, the CVD method. It isparticularly preferable that the SiO₂ film be formed under a reducedpressure at a temperature of 450° C. by a silane-acid reaction, sincemigration of reaction atoms does not occur, with the result that only anegligible amount of SiO₂ is deposited on the bottom of the trench 25,as shown in FIG. 6B.

In a subsequent step, as shown in FIG. 6C, the overall surface of thesubstrate is etched back by the RIE, thereby removing the undoped Sifilm 28 formed on the bottom of the trench 25. The etching-resistivemask 29 is removed by NH₄ etching or the like.

Then, an insulation film formed of AsSG or PSG doped with an N-typeimpurity is formed in the space bore remained in the trench 25 by theCVD or the like. The impurity concentration can be about 10¹⁸ -10²⁰/cm³. Thereafter, this insulation film is etched back by the RIE so thatthe surface of the film is on a level with the bottom surface of thegate electrode 23, thereby forming a first N-doped film 30 as shown inFIG. 6D.

An insulation film made of BSG (Boron-Silicate Glass) doped with aP-type impurity to a concentration of about 10¹⁶ -10¹⁸ /cm³ is depositedon the first N-doped film 30 by the CVD method or the like. Then, thisinsulation film is etched back by the RIE method so that the surface ofthe film is on a level with the top surface of the gate electrode 23,thereby forming a P-doped film 31. Further, an insulation film dopedwith an N-type impurity to a concentration of about 10¹⁸ -10²⁰ /cm³ isdeposited on the P-doped film 31 in the same manner as in the case ofthe formation of the first N-doped film 30. As a result, a secondN-doped film 32 is formed.

Through the aforementioned deposition and removal steps, the firstN-doped film 30, the P-doped film 31 and the second N-doped film 30 aresuccessively formed in the trench 25. In other words, three layers arecoaxially formed in the trench 25: an outermost layer consisting of theinsulation films 26 and 27; a middle layer of the undoped Si film 28;and a central layer consisting of the doped films.

The substrate having the deposited trench 25 is subjected to heattreatment at a temperature of about 800° to 1000° C. As a result, theN-type and P-type impurities doped in the insulation films 30 to 32 arediffused into the undoped Si film 28 which is in contact with the outerperiphery of the films 30 to 32. Then, the substrate is subjected to anetching process using NH₄ F, thereby removing the doped insulation films30, 31 and 32 in the trench 25, forming a center bore as shown in FIG.6F.

As a result, a P-type diffusion region 34 is formed on the gateinsulation film 26 on the inner sidewall of the gate electrode 23.N-type diffusion regions 35 and 36 are respectively formed on and underthe P-type diffusion region 34. Thus, a ring channel TFT 33, comprisinga conductive film (including the P-type diffusion region 34 serving as achannel, the N-type diffusion region 35 serving as a drain and theN-type diffusion region 36 serving as a source), the gate insulationfilm 26 and the gate electrode 23, is formed. The drain region 35 isconnected to a bit line 40.

Subsequently, as shown in FIG. 6G, a third insulation film 37 made ofSiO₂ or the like is formed on the interior surface of the trench 25 andthe surface of the bit line 40. For example, thermal oxidation can beemployed to form the third insulation film 37. It is preferable that thethickness of the third insulation film 37 be thinner than that of thecapacitor insulation film 27, for example, about 8-9 nm. Further, an A1film 38 is formed on the third insulation film 37 above the bit line 40.It is preferable that the A1 film be formed by a sputtering method,since only a negligible amount of A1 film is deposited on the bottom ofthe trench 25.

Thereafter, the overall surface of the substrate is etched back by theRIE method, thereby removing that portion of the third insulation film37 which is formed on the bottom of the trench 25. Further, the A1 film38 is removed by a sulfuric acid-type solvent or a phosphoric acid, withthe result that a structure as shown in FIG. 6H is obtained. Then, theinterior of the trench 25 and the surface of the third insulation film37 are washed with an aqueous solution of hydrogen peroxide.

In a subsequent step, a conductive column 39 made of monocrystalline Sior the like doped with a P-type impurity, such as B, to a concentrationof about 10¹⁶ -10¹⁹ /cm³ is formed in the center bore of the trench 25by a selective epitaxial growth (SEG) technique or the like.

The conductive column 39 can be formed by any other method, so long asit is formed in the trench 25, while an impurity is being introducedtherein. For example, a conductive column 39 can be formed of a metal,in which case a barrier metal layer made of, for example, Ti/N, isformed in a lower portion of the trench, and an upper portion made ofmetal, such as A1, is formed on the barrier metal layer.

Finally, the surface of the conductive column is polished, so that theconductive column 39 is filled in the trench 25, as shown in FIG. 7A,thereby obtaining a DRAM cell according to the present invention.

As shown in FIG. 7A, the DRAM cell of this embodiment comprises the ringchannel TFT 33 including the drain region 35 connected to the bit line40, the source region 36, the channel region 34, the gate insulationfilm 26 and the gate electrode 23 serving as a word line. It alsocomprises a capacitor 42 including the silicon substrate 21, thecapacitor insulation film 27, the source region 36 serving as a chargestorage layer, the third insulation film 37 and the conductive column39.

FIGS. 7B and 7C are cross-sectional views of the DRAM cell respectivelytaken along the lines 7B--7B and 7C--7C in FIG. 7A. In the ring channelTFT 33, as shown in FIG. 7B, the gate insulation film 26, the P-typediffusion region 34 serving as a channel region and the third insulationfilm 37 are formed in this order on the inner circumferential surface ofthe gate electrode 23. Further, the column 39 made of doped Si is filledin a region surrounded by the third insulation film 37.

In the capacitor 42, as shown in FIG. 7C, the charge storage layer,i.e., the source region (N-type diffusion region) 36 and the thirdinsulation film 37 are formed in this order on the inner circumferentialsurface of the capacitor insulation film 27. Further, the column 39 madeof doped Si is filled in a region surrounded by the third insulationfilm 37.

According to the first embodiment, the Si column 39 doped with theP-type impurity is filled in a region surrounded by the ring-shapedchannel region (P-type diffusion region) 34 so as to be brought intocontact with the substrate 21 at its bottom. With this structure, a backgate bias can easily be applied to the channel region by applying a biasto the Si column 39. Hence, the cut-off characteristic of the transistorcan be improved.

Moreover, the third insulation film 37 is formed between the conductiveSi column 39 and a cylindrical conductive film including the regions 34,35 and 36 in which the impurities are diffused. The area of thecapacitor 42 is therefore increased as compared to that in theconventional device. As a result, the capacitance of the capacitor canbe increased. If the third insulation film 37 is thinner than thecapacitor insulation film 27, the capacitance can be much more increasedthan that in the case of the conventional device.

EXAMPLE 2

FIGS. 8A to 8E are cross-sectional views showing steps of fabricating asemiconductor device according to a second embodiment of the presentinvention.

First, the structure shown in FIG. 8A is formed in the same steps as inExample 1, as described above with reference to FIGS. 4A to 6E. Then,monocrystalline Si doped with a P-type impurity, such as B, to aconcentration of about 10¹⁶ -10¹⁸ /cm³ is formed in the trench 25 (onthe doped regions 34, 35 and 36) and an upper surface of the bit line 40by a selective epitaxial growth (SEG) technique. As a result, a P-typeepitaxial layer 41 is formed, as shown in FIG. 8B.

Finally, the P-type epitaxial layer 41 is polished by CMP (ChemicalMechanical Polishing), until the surface of the bit line 40 is exposedand a P-type Si column 39 is filled in the trench 25 as shown in FIG.8C.

In this embodiment, since the cylindrical conductive film including thedoped regions 34, 35 and 36 is in direct contact with the conductivecolumn 39, it is preferable that the type of the impurity used in theSEG be the same as that of the impurity diffused in the channel region34.

As a result, a DRAM cell having one transistor and one capacitor can beobtained.

As shown in FIG. 8C, the DRAM cell of this embodiment comprises a ringchannel TFT 33 including the drain region 35 connected to the bit line40, the source region 36, the channel region 34, the gate insulationfilm 26 and the gate electrode 23 serving as a word line. It alsocomprises a capacitor 43 including the silicon substrate 21, thecapacitor insulation film 27, the source region 36 serving as a chargestorage layer, and the conductive column 39.

FIGS. 8D and 8E are cross-sectional views of the DRAM cell respectivelytaken along the lines 8D--8D and 8E--8E in FIG. 8C. In the ring channelTFT 33, as shown in FIG. 8D, the gate insulation film 26 and the P-typediffusion region 34 serving as a channel region are formed in this orderon the inner circumferential surface of the gate electrode 23. Further,the column 39 made of Si doped with a P-type impurity is filled in aregion surrounded by the P-type diffusion region 34.

In the capacitor 43, as shown in FIG. 8E, the charge storage layer,i.e., the source region (N-type diffusion region) 36 is formed on theinner circumferential surface of the capacitor insulation film 27.

Further, the column 39 made of Si doped with the P-type impurity isfilled in a region surrounded by the source region 36.

In the DRAM cell of the second embodiment, the bottom of the Si column39 doped with P-type impurity is in contact with the substrate 21 andpart of the side surface of the Si column 39 is in contact with thechannel region 34, with this structure, since the potential of thesilicon substrate 21 can be directly applied to the channel region 34,the cut-off characteristic of the transistor can be further improved.

Moreover, in the capacitor 43 of the DRAM cell of this embodiment, partof the side surface of the P-type Si column is in direct contact withthe N-type cell capacitor region 36. With this structure, since a PNjunction capacitance obtained by this P-N junction is added to thecapacitance of the capacitor 43, the cell capacitance is much moreincreased than that of the conventional device.

EXAMPLE 3

FIGS. 9A to 9C are cross-sectional views showing steps of fabricating asemiconductor device according to a third embodiment of the presentinvention.

Insulation films 26 and 27 are formed in the same steps as in Example 1and thereafter the capacitor insulation film 27 formed on the bottom ofthe trench 25 is removed by the RIE method, as described above withreference to FIGS. 4A to 6A. Subsequently, in the same manner as inExample 1, a cylindrical undoped Si film is formed in the trench, asshown in FIG. 6B. Insulation films 30, 31 and 32 doped withpredetermined impurities are successively formed to predetermined levelsin the cylindrical film, as shown in FIGS. 6D and 6E. The impurities arediffused into the cylindrical undoped Si film by a heat treatment,thereby forming diffusion regions 34, 35 and 36. Then, the insulationfilms situated in the center bore of the cylindrical film are removed byan etching process using NH₄. Thereafter, a third insulation film 37 isformed in the interior surface of the trench and only the portion of thefilm 37 formed on the bottom of the trench is removed.

Then, monocrystalline Si doped with a P-type impurity, such as B, to aconcentration of about 10¹⁶ -10²⁰ /cm³ is deposited in a regionsurrounded by the insulation film 37 in the trench 25 by the selectiveepitaxial growth (SEG) technique.

Finally, the surface of the conductive Si layer is polished by CMP(Chemical Mechanical Polishing), until the surface of the bit line 40 isexposed. A column 39 formed of the conductive Si layer is thus filled inthe trench 25 as shown in FIG. 9A.

As a result, a DRAM cell having one transistor and one capacitor can beobtained.

As shown in FIG. 9A, the DRAM cell of this embodiment comprises a ringchannel TFT 33 including the drain region 35 connected to the bit line40, the source region 36, the channel region 34, the gate insulationfilm 26 and the gate electrode 23 serving as a word line. It alsocomprises a capacitor 42 including the silicon substrate 21, thecapacitor insulation film 27, the source region 36 serving as a chargestorage layer, the third insulation film 37 and the conductive column39.

FIGS. 9B and 9C are cross-sectional views of the DRAM cell respectivelytaken along the lines 9B--9B and 9C--9C in FIG. 9A. In the ring channelTFT 33, as shown in FIG. 9B, the gate insulation film 26, the P-typediffusion region 34 serving as a channel region and the third insulationfilm 37 are formed in this order on the inner circumferential surface ofthe gate electrode 23. Further, the conductive Si column 39 is filled ina region surrounded by the third insulation film 37.

In the capacitor 42, as shown in FIG. 9C, the charge storage layer,i.e., the source region (N-type diffusion region) 36 and the thirdinsulation film 37 are formed in this order on the inner circumferentialsurface of the capacitor insulation film 27. Further, the conductive Sicolumn 39 is filled in a region surrounded by the third insulation film37.

In the DRAM cell of this embodiment, similar to the first embodiment,the conductive Si column 39 doped with the P-type impurity is filled inthe region surrounded by the ring-shaped channel region (P-typediffusion region) 34 so as to be brought into contact with the substrate21 at its bottom. With this structure, a back gate bias can easily beapplied to the channel region by applying a bias to the Si column 39.Hence, the cut-off characteristic of the transistor can be improved.

Moreover, since the third insulation film is formed between theconductive Si column 39 and the N-type diffusion region 36, the area ofthe capacitor 42 is therefore increased as in the first embodiment. As aresult, the capacitance of the capacitor can be increased.

Furthermore, in the DRAM cell of this embodiment, an N⁺ region 44 isformed under the charge storage layer of the capacitor 42 as shown inFIG. 9A.

As has been described above, according to the present invention, sincethe conductive column is formed in the region surrounded by thering-shaped channel region, a back gate bias can be applied from thesubstrate to the channel region through the conductive column.Therefore, the cut-off characteristic of the transistor can be improved.

In addition, the capacitance of the capacitor can be increased by theconductive column. More specifically, if the conductive column is indirect contact with the cylindrical conductive film formed on the outercircumferential surface, the PN junction capacitance obtained by a PNjunction is added to the capacitance of the capacitor, with the resultthat the capacitance is increased. On the other hand, if an insulationfilm is formed between the conductive column and the cylindricalconductive film, the area of the capacitor is increased, with the resultthat the capacitance is increased.

Further a portion of, the cylindrical conductive film formed in thetrench functions not only the source region of the ring channel TFT butalso the charge storage layer of the capacitor. Thus, a DRAM cell havingone transistor and one capacitor is obtained.

As described above, a DRAM cell, comprising a transistor having animproved cut-off characteristic and a capacitor having an increasedcapacitance, can be provided. Therefore, it is possible to produce asemiconductor device having a high integration density. Such a DRAM cellis very valuable in the field of industry.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details, and representative devices shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

What is claimed is:
 1. A semiconductor device comprising:a semiconductorsubstrate of a first conductivity type; a first insulation film formedon a surface of said semiconductor substrate; a gate electrode formed onsaid first insulation film; a second insulation film formed on saidfirst insulation film and said gate electrode; a cylindrical gateinsulation film formed on a surface of said gate electrode which isexposed in a trench formed to extend through said second insulationfilm, said gate electrode and said first insulation film to an interiorof said semiconductor substrate; a capacitor insulation film formed on asurface of said semiconductor substrate which is exposed in said trench;a cylindrical conductive film including a region doped with an impurityof the first conductivity type and formed on said gate insulation film,a region doped with an impurity of a second conductivity type and formedon a surface of said second insulation film which is exposed in saidtrench and a region doped with an impurity of the second conductivitytype and formed on said capacitor insulation film; and a conductivecolumn formed in a region surrounded by said cylindrical conductive filmand electrically connected to said semiconductor substrate.
 2. Thesemiconductor device according to claim 1, wherein said conductivecolumn is made of monocrystalline silicon doped with an impurity.
 3. Thesemiconductor device according to claim 1, wherein a cylindrical thirdinsulation film is formed between said cylindrical conductive film andsaid conductive column.
 4. The semiconductor device according to claim3, wherein said third insulation film is thinner than said capacitorinsulation film.
 5. The semiconductor device according to claim 3,wherein said conductive column is doped with an impurity of the firstconductivity type.
 6. A semiconductor device comprising:a semiconductorsubstrate of a first conductivity type; a first insulation film formedon a surface of said semiconductor substrate; a gate electrode formed onsaid first insulation film; a second insulation film formed on saidfirst insulation film and said gate electrode; a cylindrical gateinsulation film formed on a surface of said gate electrode which isexposed in a trench formed to extend through said second insulationfilm, said gate electrode and said first insulation film to an interiorof said semiconductor substrate; a capacitor insulation film formed on asurface of said semiconductor substrate which is exposed in said trench;a cylindrical conductive film including a region doped with an impurityof the first conductivity type and formed on said gate insulation film,a region doped with an impurity of a second conductivity type and formedon a surface of said second insulation film which is exposed in saidtrench and a region doped with an impurity of the second conductivitytype and formed on said capacitor insulation film; a cylindrical thirdinsulation film formed on an inner surface of said cylindricalconductive film; and a conductive column formed in a region surroundedby said cylindrical third insulation film and electrically connected tosaid semiconductor substrate.
 7. The semiconductor device according toclaim 6, wherein said conductive column is made of monocrystallinesilicon doped with an impurity.
 8. The semiconductor device according toclaim 6, wherein said third insulation film is thinner than saidcapacitor insulation film.
 9. The semiconductor device according toclaim 6, wherein said conductive column is doped with an impurity of thefirst conductivity type.
 10. A semiconductor device comprising:asemiconductor substrate of a first conductivity type; a first insulationfilm formed on a surface of said semiconductor substrate; a gateelectrode formed on said first insulation film; a second insulation filmformed on said first insulation film and said gate electrode; acylindrical gate insulation film formed on a surface of said gateelectrode which is exposed in a trench formed to extend through saidsecond insulation film, said gate electrode and said first insulationfilm to an interior of said semiconductor substrate; a capacitorinsulation film formed on a surface of said semiconductor substratewhich is exposed in said trench; a cylindrical conductive film includinga region doped with an impurity of the first conductivity type andformed on said gate insulation film, a region doped with an impurity ofa second conductivity type and formed on a surface of said secondinsulation film which is exposed in said trench and a region doped withan impurity of the second conductivity type and formed on said capacitorinsulation film; and a conductive column, doped with an impurity of thefirst conductivity type, formed within said cylindrical conductive filmand in direct contact with an inner surface of said cylindricalconductive film, said conductive column being electrically connected tosaid semiconductor substrate.
 11. A semiconductor memory deviceincluding a data storage capacitor and a thin film switching transistor,said semiconductor memory device comprising:a semiconductor substrate ofa first conductivity type; a first insulation film formed on saidsemiconductor substrate; a first conductive film formed on said firstinsulation film; a second insulation film formed on said firstconductive film; a trench formed through said second insulation film,said first conductive film and said first insulation film, said trenchextending into said semiconductor substrate; a third insulation filmformed on said first conductive film exposed by said trench; a fourthinsulation film formed on said semiconductor substrate exposed by saidtrench; a cylindrical second conductive film, having a center bore,formed in said trench and including a first portion of a secondconductivity type formed on said second insulation film exposed by saidtrench, a second portion of the first conductivity type formed on saidthird insulation film, and a third portion of the second conductivitytype formed on said fourth insulation film; and a third conductive filmformed in said center bore of said cylindrical second conductive filmand electrically connected to said semiconductor substrate, wherein saidthin film switching transistor comprises a gate electrode constituted bysaid first conductive film, a gate insulating film constituted by saidthird insulation film, a channel region constituted by said secondportion of said cylindrical second conductive film, and source/drainregions constituted by said first and third portions of said cylindricalsecond conductive film, and wherein said data storage capacitorcomprises a data storage electrode constituted by said third portion ofsaid cylindrical second conductive film and a plate electrodeconstituted by said semiconductor substrate and said third conductivefilm.
 12. The semiconductor memory device according to claim 11, furthercomprising:a fifth insulation film disposed between said cylindricalsecond conductive film and said third conductive film.
 13. Thesemiconductor memory device according to claim 12, wherein the thicknessof said fifth insulation film is less than the thickness of said fourthinsulation film.
 14. The semiconductor memory device according to claim12, wherein the thickness of said fifth insulation film is about 8 to 9nanometers.
 15. The semiconductor memory device according to claim 11,wherein said third conductive film comprises a conductive film dopedwith an impurity of the first conductivity type which directly contactssaid cylindrical second conductive film.
 16. The semiconductor memorydevice according to claim 11, wherein said third conductive filmcomprises monocrystalline silicon.
 17. The semiconductor memory deviceaccording to claim 11, further comprising:an impurity region of thesecond conductivity type formed in said semiconductor substrate andelectrically connected to said third portion of said cylindrical secondconductive film.
 18. The semiconductor memory device according to claim11, wherein said first portion of said cylindrical second conductivefilm is connected to a bit line.